Pressure engineering method enhances efficiency of 2D semiconductor-based transistors

The manipulation of mechanical pressure in supplies, often known as pressure engineering, has allowed engineers to advance electronics over the previous a long time, as an illustration enhancing the mobility of cost carriers in gadgets. Over the previous few years, some research have tried to plan efficient methods to govern pressure in two-dimensional (2D) semiconductors which can be suitable with current industrial processes.

Researchers at Stanford College not too long ago launched a CMOS-compatible method to engineer the tensile pressure (i.e., stretchiness) in monolayer semiconductor transistors.

This method, outlined in a paper printed in Nature Electronics, depends on the usage of silicon nitride capping layers that may impart pressure on monolayer molybdenum disulfide (MoS₂) transistors built-in on silicon substrates.

“We began brainstorming this concept way back to 2020, when our analysis group was pursuing an earlier effort to use pressure by mechanically bending the samples,” Eric Pop, senior creator of the paper, advised Tech Xplore.

“On the time, there have been only a few experimental demonstrations of utilizing pressure to enhance efficiency in two-dimensional (2D) materials transistors, and none completed this utilizing strategies which can be industry-friendly.

The principle goal of the latest work by Pop and his colleagues was to attempt to determine new promising pressure engineering methods rooted within the processing of typical silicon transistors, which may very well be utilized to 2D supplies. After delineating one in every of these methods, they efficiently utilized it to a 2D MoS₂-based transistor for the very first time.

“Drawing inspiration from the silicon {industry} within the early 2000s, our technique makes use of skinny silicon nitride capping layers (a cloth extensively utilized in {industry}) to use pressure to the 2D semiconductor transistor,” defined Pop. “The stress in these movies will be exactly tuned, and they are often deposited at comparatively low temperatures, which is advantageous for numerous industrial functions.”

Firstly, the researchers processed 2D semiconductors utilizing well-established fabrication methods and used them to create transistors. They added silicon nitride movies on the finish of the processing, as this allowed them to obviously pin-point the impact these movies had on the pressure within the transistors, distinguishing it from results linked to temperature modifications and doping.

“The primary notable contribution of this work is the experimental demonstration that process-induced pressure (i.e. pressure attributable to numerous fabrication steps throughout transistor fabrication) exists in these 2D materials transistors, and it may be leveraged to extend the on-state present utilizing methods which have been beforehand used for silicon transistors,” mentioned Pop.

“Importantly, we additionally supplied a simulation-based roadmap of how this pressure modifications as we shrink these gadgets to technologically-relevant dimensions, and located that pressure holds nice promise on this regime.”

In preliminary assessments, the researchers discovered that their pressure engineering method enabled an enhancement within the efficiency of 2D MoS₂ transistors, whereas additionally lowering each transistor channels and contacts. Sooner or later, their work may contribute to the event of smaller and higher performing 2D semiconductor-based transistors.

In the meantime, Pop and his colleagues plan to proceed testing and enhancing their proposed pressure engineering method. Additionally they plan to analyze the results of pressure on different 2D semiconductors past monolayer MoS_2.

“On the basic stage, we’re utilizing versatile substrates to check the impact of pressure in different 2D semiconductors that are much less well-understood,” added Pop.

“Moreover, we’re investigating different sources of process-induced pressure such because the impression of metallic deposition on 2D supplies (a key step throughout system fabrication). Lastly, we’re engaged on extending this method to p-type 2D transistors (versus the n-type gadgets used on this examine), as a result of their efficiency at present lags behind that of the n-type gadgets.”

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